It is desirable in the semiconductor industry to produce structures of as small size as possible in order to lower the total cost and allow the increase of complexity of a product.
One limitation to reducing of integrated circuit die size is the requirement of keeping enough distance between the semiconductive substrate contacts and adjacent conductive structures to prevent shorting of adjacent structures to the contacts due to misalignment between the contacts and the adjacent structures. Misalignment can occur during masking of the contact locations.
Another limitation is the size of the contact opening itself Contact openings through a layer or layers applied to the substrate are typically formed by applying a photoresist layer on the layer or layers and patterning the photoresist layer with a mask having transparent portions located above the desired contact openings. The photoresist is exposed to light at locations beneath these transparent portions in the photolithographic mask. The mask is removed, the photoresist is developed and the developed portions of the photoresist are removed. Scattering of light at the edges of the mask causes exposure of a region of photoresist noticeably larger than the mask transparent regions.
Because the wave length of light used to expose the photoresist is on the same order as the size of transparent regions in the mask, in order to allow light to penetrate through the transparent regions of the mask, the transparent regions must be of a certain minimum size (the photolithographic limit), therefore the photoresist opening must be of a larger size than the photolithographic limit, at minimum.
FIGS. 1a-1e and 2a-2e shown top and side views of a prior art process for forming a semiconductor structure, in this case, MOS transistor structure 100. As shown in FIGS. 1a and 2a, polycrystalline silicon gate 1 has been formed on a thin insulation layer 2 applied to substrate 2. Lightly doped source and drain regions 6a and 6b have been formed using gate 1 and field oxide 4 as self-aligning masks. Subsequently, side-wall spacers 5 have been formed adjacent gate 1. Sidewall spacers 5 can be formed by either chemical vapor deposition of oxide on the wafer surface followed by a blank anisotropic etch to remove oxide on horizontal surfaces, or by thermally growing oxide on the substrate and polysilicon gates, again followed by an anisotropic etch.
Subsequently, as shown in FIGS. 1b and 2b, source/drain regions 7a and 7b are implanted using sidewall spacers 5 and field oxide 4 as masks. Subsequently, a layer of oxide 8 is formed over the surface of the structure. As shown in FIGS. 1c and 2c, photoresist layer 9 is formed on oxide layer 8. Mask 101 is then located above structure 100, with mask transparent regions 11a and 11b positioned above source/drain regions 7a and 7b. Photoresist regions 9a and 9b are then exposed and removed. There is scattering of the exposing light at edges of transparent regions 11a and 11b of mask 101, causing the exposed regions 9a and 9b of photoresist layer 9 to be larger at each side by an amount "r" than transparent regions 11a and 11b of mask 101. Thus when photoresist regions 9a and 9b are removed, the exposed regions 8a and 8b of oxide layer 8 are larger by 2r than transparent mask regions 11a and 11b. Additionally, because mask 101 is not self-aligned with structure 100, allowance must be made for possible misalignment of mask 101. It is essential that conductive material which will extend into openings of oxide layer 8 not contact adjacent gate 1 (or other adjacent structures in other parts of the integrated circuit not shown). Thus a clearance which allows for both sufficient insulation between opening 8a or 8b and gate 1 and for a misalignment tolerance level must be provided. FIG. 3 shows an unacceptable situation in which exposed contact region 8a is misaligned to the point that gate 1 is exposed. In this case, conductive material applied subsequently will contact gate 1, causing a gate 1 to source/drain 7a short, and a failed structure. Clearance d of FIG. 2d is provided to assure both adequate insulation between gate 1 and source/drain regions 7a and 7b and to allow for misalignment. Each via region shown in FIGS. 1e and 2e must be of a size to accommodate tolerance d, enlargement factor 2r, and the size of the transparent regions such as 11a of mask 101. According to one set of design rules, photolithography requirements place the minimum size of mask transparent region 11a at 1.2 microns. The light enlargement r is 0.1 micron on each side for a total enlargement of 0.2 micron, the tolerance for misalignment is 0.3 microns and the side wall insulation thickness is 0.2 micron for a total required allotment of via spacing of 1.9 microns. It is of course desirable to reduce this via spacing.